It is known that semiconductor working memories, such as those used in data processing systems, are built up with a plurality of memory modules to incrementally increase their capacity. For such memories the problem of a fast and efficacious module selection arise; i.e., the selection operation implies a time waste which, if at all possible, must be avoided.
Conceptually a memory address, expressed in binary code, comprises a first bit field which references an addressable location or "entry" in each of a plurality of modules and a second bit field which references one among the several modules which form the memory. This second field must be decoded by a decoding circuit to provide a selection signal of one module, with exclusion of the others.
The time loss resulting from this decoding operation is made worse in systems where virtual memory addressing is used and the memories are structured for the immediate addressing of "rows" and the subsequent addressing of "columns". In these systems the address generated by a processor requiring a memory operation is of logical type and comprises an "offset" field and a logical page address field. The "offset" field coincides with a corresponding "offset" field of the physical address, but the logical page address field must be converted for its use in a physical page address. This conversion is typically performed by an address management unit or MMU.
When this address structure is used, it is possible to immediately start a memory operation by providing the memory system with the "offset" field, and subsequently forwarding the physical page address. The physical page address substantially comprises a field corresponding to a column address and a field which identifies a module (which module field must be decoded).
In order to avoid time losses involved in decoding and further, in case of logical addresses, due to the delay in the availability of the field to be decoded, the prior art approaches have employed the simultaneous activation of all the memory modules, the selection being performed at the output level by enabling the output of the selected module only. This enabling operation may be performed at the end of the memory cycle, when the address information required for selection is already available.
This prior art approach, however effective, has heavy trade offs. The activation of all memory modules results in substantial power consumption and thus requires power supplies sized for the maximum foreseen memory capacity. Further, if write operations of the "off line" type are performed, (i.e. the write operation, once started, is completed by the memory system without any form of control by the processor), it becomes impossible to exert a timely control on the operation result.
Still further, the write operation may reference an entry which exceeds the installed memory capacity. (In fact, it is clear that the presence or absence of a selected memory module may be verified only when the logical address has been converted into a physical address and only when the physical address has been decoded to produce a module selection signal, with circuits and methods an example of which is provided by U.S. Pat. No. 4,592,011.) The resulting "overmemory" signal becomes available too late for consideration. Thus, either the protection is given up or the off line write operations are given up or complex expedients have to be provided.
The present memory subsystem with predictive module selection of the present invention overcomes these drawbacks of prior art memory subsystems employing a plurality of addressable modules.